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A relative newcomer in the embedded digital signal processing industry, DSP vendor 3DSP Corp. (Irvine, CA), has unveiled its SP-5, fixed-point hard and soft cores. Targeting Internet, communications, and multimedia designs, the SP-5 DSP cores are currently available via licensing agreements to system-on-a-chip (SOC) and ASIC builders.

3DSP's core features what the firm calls SuperSIMD (a super scalar single instruction multiple data architecture). It enables up to 3.2 billion RISC equivalent instructions/second, or 600 million MAC (multiply-accumulate) instructions/second. Power dissipation is typically 300 mW.

3DSP says its SuperSIMD provides the SP-5 with a unique memory-to-register-file feature as well as the load-and-store architecture commonly found in DSPs. The SP-5 DSP core automatically handles data dependencies and hazards, reducing the amount of memory required and system design costs at production. It also increases ease of programming.

The SP-5 is one of the smallest DSP cores. It's die measures 2.4mm square. Despite its size, the SP-5 is a high-performance core with the processing power to handle demanding operations of next-generation digital appliances. The core is completely synthesizable, permitting it to be integrated into any silicon foundry process and to be readily reconfigured.

Contact Kan Lu, president, at 3DSP Corp., 16735 Von Karman, Suite 100, Irvine, CA 92614. Phone: (949) 260-0156. Fax: (949) 260-0151.

Edited by Alex Mendelsohn

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