TestBencher Pro

TestBencher Pro generates reactive VHDL and Verilog test benches and bus-functional models from language-independent timing diagrams. The generated test benches are capable of applying different stimulus vectors depending on simulation response so that the test bench functions as a behavioral model of the environment in which the system being tested will operate. An excellent tool for testing large FPGA and ASIC designs.

Surveys of HDL users have indicated that the generation of complex HDL test benches typically consumes 35% of the entire front-end ASIC design cycle. In an effort to reduce test bench creation time SynaptiCAD has released its newest product, TestBencher Pro, a self-testing test bench generator for VHDL and Verilog based on SynaptiCAD's previous product, WaveFormer. Test benches generated by TestBencher Pro include input stimulus vectors and extra code that checks simulation output for correctness. The generated test benches are capable of applying different stimulus vectors depending on simulation response so that the test bench functions as a behavioral model of the environment in which the system being tested will operate. Using TestBencher Pro, bus-functional microprocessor interfaces can be modeled with only a few lines of code. TestBencher Pro also provides an automated method for checking large ASIC simulation runs.

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