Genesys Testware, Inc. (Fremont, CA) added VHDL support to its TestCore family of cores for System on Chip (SOC) test automation. The product line includes Memory BistCore (Built-In Self-Test [BIST]) of embedded memories); Boundary ScanCore (board test, core test integration and test pattern reuse); and Logic BistCore (BIST of hard cores and on-chip logic). According to the company, each product is a library of parameterized, synthesizable, register-transfer level (RTL) designs..
The product line features parameterized self-checking testbenches, which can be used to verify the operation of the BIST circuit using any VHDL (IEEE 1076-1993) or Verilog (IEEE 1364-1995) compliant simulator.
The products adhere to the new paradigm of using cores to test cores in a large ASIC or SOC. In a typical SOC test tool process, the user specifies the parameters of the core to a program, which generates a test circuit in regular RTL. In the new SOC test core process, the user customizes a highly parameterized RTL test circuit by changing core parameters in Verilog or VHDL. This new paradigm enables improvements in ease of use and flexibility by eliminating the RTL test circuit generation process and through RTL integration of test circuitry into an SOC.
No tools or libraries are required since it is a completely HDL based solution.
The company added a highly reconfigurable Built-In Self-Test, Diagnosis and Repair (BISTDR) solution for embedded DRAMs to Memory BistCore . Both address and data repair with multiple user selectable self-repair strategies. At-speed BIST is used for detecting delay defects which are common in deep sub-micron technology. It is now also possible to generate optimized test patterns in WGL format for 1149.1 compliance checking, pin parametric tests, at-speed scan chain tests, BIST circuit internal tests, and BIST operation from Boundary ScanCore . This allows IC designers to implement a comprehensive SOC test methodology in a process, foundry and tester independent manner.