Altera and PLD Applications Start Shipping 64-Bit, 66 MHz PCI Cores

Altera Corp. announced the immediate availability of two sets of 64-bit, 66 MHz PCI cores for use with Altera FLEX 10KE programmable logic devices (PLDs). The new cores allow designers to begin developing new, high-performance products based on the 64-bit, 66 MHz PCI specification.

Two sets of 64-bit, 66 MHz cores are available. The first is Altera's own 64-bit, 66 MHz PCI Master/Target MegaCore function. Fully compliant with the PCI Rev. 2.2 specification and extensively verified at ten beta customer sites, the core is parameterized to allow designers to focus their resources on improving and differentiating their products. To guarantee PCI compliance, Altera has performed extensive hardware verification and simulation on the PCI function. The core is optimized for Altera's FLEX 10KE architecture.

The second PCI core is from PLD Applications, a member of the Premier Altera Megafunction Partners Program (AMPPM). This new VHDL source code version joins PLD Applications' wide range of PCI cores designed for Altera's programmable logic devices.

Altera's parameterized 64-bit, 66 MHz Master/Target PCI MegaCore, also referred to as PCI/C, is fully compliant with PCI Specification Rev. 2.2 timing and functional requirements. The core has been rigorously tested on the Phoenix Technologies' Testbench, Hewlett-Packard's PCI Bus Analyzer, and Altera's PCI development board.

The PCI/C Master/Target MegaCore function features independent master and target operation, allowing maximum throughput (up to 528 Mbytes/sec) and efficient usage of the PCI bus. The core's parameters can be modified upon instantiation to provide scalability, adaptability, and efficient silicon implementation. Other features include zero-wait-state memory read/write for both master and target, support for all the required PCI bus commands, dynamic negotiation and response to 32- or 64-bit transactions, 64-bit addressing; host bridge support, Compact PCI hot swap capability, and expansion ROM.

The VHDL-based PCI Target builds on the success of PLD Applications' extensive selection of PCI Master/Target cores. The VHDL-sourced version features full compliance with PCI Local Bus Specification Rev. 2.2. The core also features fully synchronous design, easy customization via Altera's MegaWizard Plug-In, full plug-and-play support, and extensive hardware test using PLD Applications' PCI prototyping boards. Features that can be customized using the MegaWizard include the 64-bit addressing and dual-address cycle command, simplified interrupt signals, support for 64-bit base addresses, a new expansion ROM BAR, a capability pointer, and a Cardbus CIS pointer. The core supports unlimited burst memory transfers, zero-wait-state insertion, 64-bit data transfer and 64-bit addressing, and multiple 64- or 32-bit base address registers.