Product/Service

Analog-To-Digital Converter

Source: Texas Instruments
The high-speed, analog-to-digital converter (ADC) features simultaneously-sampled dual inputs and single or dual eight-bit buses with one ADC core that operates at twice the sampling rate to internally multiplex the two inputs
Texas Instrumentseed, analog-to-digital converter (ADC) features simultaneously-sampled dual inputs and single or dual eight-bit buses with one ADC core that operates at twice the sampling rate to internally multiplex the two inputs, reducing mismatch errors compared to devices that use two ADCs. The eight- bit, 40 megasamples-per-second (MSPS), low-power converter enables designers to closely match conversions from two channels in systems involving simultaneous In-phase and Quadrature (I & Q) baseband sampling, such as wireless local loop systems, cable modems, set top boxes and test instrumentation. The device, designated the THS0842, is a 3.3 V device and consumes 275 mW of power, which makes it suited for portable, battery-operated applications. It also has a stand-by power mode, which further reduces power consumption to as little as 11 mW.

The converter has a wide analog input bandwidth of 600 MHz and a good spurious free dynamic range (SFDR) of 52 dB and 44 dB signal to noise ratio (SNR) when sampling a 20MHz input signal. With these characteristics, the device is suited for communications applications, including those where undersampling might be used.

The dual inputs of the converter, which can be either differential or single-ended, are sampled simultaneously and are internally multiplexed to the single ADC core for conversion. The input choices provide flexibility and are well suited for transformer-coupled operations.

The output bus is hardware-selectable for single or dual eight-bit bus operations, allowing the designer to choose between a single high-speed data bus and a wider dual bus mode that separates the two input channels conversion results. Both positive and negative edge latch signals are provided in either bus mode to simplify system design and connection to demodulation ASICs. The edge transitions of the latch signals are centered with respect to the data.

<%=company%>, SC-00007 Literature Response Center PO Box 954 Santa Clarita, CA 91380. Phone: 800-477-8924, ext. 4500.