Design Team Uses Soft CPU Core to Speed System-on-a-Chip To Market
How did one successful ASIC design team sidestep C compilers and debuggers as it developed a single-chip controller used to support flat-panel displays? Engineers at fabless semiconductor company Pixelworks did it using acquired intellectual property and EDA tools—and finished the IC in just 15 months.
•Cutting Component Count
•No Previous Experience
•Core Re-Use Issues
•Virtual Tools Reigned
Pixelworks (Tualatin, OR) is a company whose strategy is to offer OEMs a route to cost effective fast-turn flat panel display (FPD) integration. The firm's core competencies include high-speed digital design, mixed-signal and video processing, system-on-a-chip (SOC) design, and product planning and marketing services. Pixelworks even helps OEMs with product sales and channel development.
Pixelworks knew that, after dominating the display marketplace for more than a half century, the venerable cathode ray tube's dominant position in computer and video displays was nearing an end. CRTs were being displaced by an onslaught of FPD technologies.
The company looked at the $25 billion market for computer monitors and liked what it saw. It knew that LCD monitor sales alone were exploding, from 161,000 units in 1996 to more than three million this year. Nearly 12 million would be in use by 2001.
The application of FPD display technology in other application areas, such as multimedia projectors, was equally as explosive. To assist OEMs, and carve out a niche for itself, Pixelworks decided to design an advanced image display chip for the burgeoning FPD arena.
"The goal of developing our chip--which we would call the PW364 ImageProcessor IC--would be to offer OEMs a single device that could replace the numerous components that connect an FPD to an image source," explains Bob Greenberg, the firm's vice president of product development. "We knew such a chip would be attractive to OEMs, whether they were designing a computer, a DVD player or a digital television."
Greenberg also knew a next-generation image processor chip would have to achieve a high level of integration to be cost effective. That way, OEMs would clearly see it as a route to improved performance, reduced cost, and lowered dissipation--all in a small footprint device.
The PW364 was planned as an interface between a PC's analog RGB output, for example, and LCDs or other flat panel systems such as an LCD desktop monitor, or a projector, or a plasma display. To get the ball rolling, Greenberg charged a design team with outlining the chip's specifications, and determining its functionality.
His team would also judge the capacity and speed of critical design elements, and handle the selection of a core microprocessor. A processor was needed in order to program internal registers and draw on-screen menus, or OSDs.
Nobody at Pixelworks had ever integrated a microprocessor into an ASIC, so several challenges needed to be addressed. What would the process be for integrating an intellectual property (IP) core with pre-existing logic? Also, could Pixelworks be sure the IP processor core would work--before first silicon?
Another question facing Greenberg and the Pixelworks team was whether its software engineers could start the chip's software in parallel with hardware development. Moreover, how would the code be debugged once hardware was available? These questions loomed.
There was another consideration too. The team realized that many embedded applications required only modest CPU performance. "That's why eight-bit and 16-bit microcontrollers still out-ship 32-bit CPUs," notes Greenberg. "In these applications, software development tools often determine processor selection, not the technology of the processor itself."
Satisfactorily addressing these concerns, and agreeing that a 16-bit microcontroller was the way to go, the team looked at 8086-compatible cores. Its reasoning was that software development tools and engineering expertise for hard and soft 8086s was plentiful. Tools would be mature and validated. The design team needed a core that wouldn't gobble too many gates, yet could address more than 64 kbytes of system memory.
Hard cores were available, but they would lock Pixelworks into an ASIC supplier's tools and fabrication technologies. There might be a long time lag between the Pixelworks SOC design and actual tape-out. Time-to-market was essential, so Pixelworks took a different tack.
Greenberg's team decided to use a Type V8086 Intel-8086-compatible "soft" core from VAutomation (Nashua, NH). VAutomation's soft cores are pre-designed and verified logic functions synthesizable from VHDL or Verilog RTL (register transfer level) source code. With the VHDL source code for the V8086 core in hand, Pixelworks' engineers were able to synthesize the core along with the rest of the design. They wouldn't have to worry about having a hard macro.
What's more, thanks to the soft-core approach, the design team was able to monitor the internal operation of the V8086 core during simulation. They could actually look at the 8086's AX, BX, CS, IP and SP registers to examine how the firmware was running. If need be, the team could even develop customized instructions to add to the 8086's standard instruction set.
In addition, a soft core meant that the technology would remain process independent so the company could target the latest and greatest ASIC silicon technology. The Pixelworks team didn't need a hard macro to get the performance it needed from its target technology. Place-and-route was also eased since the team didn't have to place a hard macro.
To do it, the Pixelworks engineering team configured a VHDL-based design environment under both Microsoft Windows NT and UNIX operating systems (OSs). Using these platforms, the team coded RTL blocks in VHDL. It then simulated them using Model Technology's (Portland, OR) ModelSim PE VHDL simulator running under Microsoft Windows NT.
The choices of tools and OSs proved good. Pixelworks' engineers were able to get the chip's core cranking away on code in less than one week! Indeed, the team worked all the way to full system simulation using VHDL test benches. These permit running actual code on the V8086 in the simulation environment.
Logic synthesis was done in the UNIX environment using a Synopsys (Mountain View, CA) Design Compiler.
The team realized its goal of having all of a system's high-speed video processing done in hardware. The completed PW364 ImageProcessor chip, with its DSP-based image scalers, and on-chip embedded-DRAM frame buffer for image and on-screen display (OSD) storage, worked well with the V8086 CPU core. The IC's on-chip microprocessor peripherals--timers, a UART, an interrupt controller and I/O ports--all worked.
In testing, the team ran both assembly code and C language code on the V8086 VHDL description. To accomplish that, Greenberg loaded a hex-format file into a ROM test bench. The V8086 was then taken out of Reset, where it began executing code from ROM and RAM. Debugging would take place at the source level.
Did it work out in the end? You bet! The Pixelworks design team produced a first-turn chip, a product that's now shipping in volume.
For more details, contact the vendors mentioned in this Computer OEM Online article at:
VAutomation, Inc., 402 Amherst St., Suite 100, Nashua, NH 03063. Phone: (603) 882-2282. Fax: (603) 882-1587.
Pixelworks, 8100 S.W. Nyberg Rd., Suite 100, Tualatin, OR 97062. Phone: (503) 612-6700. Fax: (503) 612-6713. Email:
Synopsys Inc., 700 East Middlefield Rd., Mountain View, CA 94043. Phone: (650) 584-5000.
Model Technology Inc., 10450 SW Nimbus Ave., Building R, Portland, OR 97223-4347. Phone: (503) 641-1340. Fax: (503) 526-5410.