DynaModel

Functional Extraction from Transistor level designs
* Transistor-level Extraction for Gate-Level Analysis
* Easily Migrate Hard IP Through Synthesis
* Resulting Model Compatible with H/W Accelerators, Cycle Based Simulators Formal Verification and Synthesis Tools * Easy to Adopt and Integrate into Flow
* Supports Aggressive Design Topologies

Product Overview
DynaModel extracts a Verilog simulation model from a full custom block. This is a zero delay simulation model. All logic in the initial transistor level design is accurately represented in the resulting Verilog model. With DynaModel, designers no longer need to use transistor level simulators (or Verilog using switch level primitives) to verify the functionality of their designs.

DynaModel understands today's most aggressive CMOS design styles, including most types of domino, self timed, or post charged domino logic. DynaModel includes DynaSpice, a SPICE engine that supports BSIM3 compatible transistor level models and the traditional SPICE model syntax. This dynamic timing analysis tool provides the accuracy of SPICE analysis with a 3-10X speed-up in performance above other SPICE engines.

DynaModel Setup
DynaModel requires a single configuration file to analyze a design. This user-supplied file in its simplest form contains the pin names arranged by type (input, output, clock and bi-directional), filename to read and write, and transistor descriptions.

Function Extraction
In order to create the functional simulation model, several steps are performed on the transistor level description. First clocks are propagated into the design as they are described in the configuration file. The clock stops propagating at the sequential elements. Next, the design is partitioned into smaller design clusters. Then using Circuit Semantics patent pending function extraction algorithm, logical descriptions are created for each design cluster. Correct simulation models are created for static CMOS logic, sequential elements, and many styles of Domino logic. Analog structures must be "black boxed" since there is no logical function to extract. These analog structures are found during the partitioning step by a user supplied pattern file. This pattern file is in the form of a spice netlist. The DynaModel Model
The generated model uses simulation primitive in most cases, UDP's (User Defined Primitives are used only when they are needed. Currently this model supports zero delay.

State elements are modeled as combination logic description with feedback loops. Simulation "fights" are modeled with a logical "X". Floating (or tristate) nodes are modeled as a "Z". Domino functions modeled as they have been designed, with separate precharge and evaluate.

Supported Design Flows
The simulation model created by DynaModel can be used as input to any Verilog compatible simulator, or hardware accelerator. This model can also be used an input to equivalence checking tools. Not all equivalence checking tools support complex CMOS design styles, please check with you tool vendor for support.

Migrating Hard Legacy Designs
One of the key applications for DynaModel is to convert a spice netlist of a hard IP block into a synthesizable Verilog description. The types of logic that are supported methodology depend on the capability by this and the synthesis tool used.

Circuit Semantics Inc., 2590 North First Street, Ste 301, San Jose, CA 95131. Tel: 408-571-4817; Fax: 408-468-1468.