Mitsubishi Samples JEDEC-Standard, 0.25-Micron, 64-Megabit DDR SDRAM

The Electronic Device Group of Mitsubishi Electronics America Inc. announced that it is sampling a 64-megabit (Mb) double data rate (DDR) synchronous dynamic random-access memory (SDRAM). Manufactured in a 0.25 µm CMOS process technology, Mitsubishi's JEDEC-standard 64-Mb DDR SDRAM supports column address strobe latencies (CL) as stringent as CL 1.5. The 64-Mb device is the first in a family of DDR SDRAMs.

DDR SDRAM offers approximately twice the speed of standard SDRAMs with little or no increase in die size. Its availability in a x4 configuration enables system-level error detection and correction more easily than do other advanced DRAM types. This capability is expected to make DDR SDRAM the most popular advanced DRAM type used for main memory in financial, scientific data, networking and communications systems.

DDR SDRAM achieves twice the clock rate of traditional SDRAM because DDR reads or writes data on both the rising and the falling clock edges of each clock cycle. It features a differential input clock and a stub series terminated logic 2 (SSTL2) interface that is faster than the interface for traditional SDRAMs, which use low-voltage transistor-to-transistor logic (LVTTL). A key reason for the speed increase of the interface is the smaller voltage swing for SSTL2, typically less than half of the voltage for traditional LVTTL. DDR SDRAM also uses a bidirectional data strobe that is synchronized to the source of each high-speed signal used.

Mitsubishi's 64-Mb DDR SDRAM product achieves clock speeds and data bandwidths as high as 133 megahertz (MHz) and 266 megabits per second (Mbps) per data pin, respectively, and is available in 16-megaword x 4-bit (16M x 4), 8M x 8, and 4M x 16 configurations. Mitsubishi's -7.5 in. specification for the memory offers a first access time of 37 ns with a 133-MHz bus at CL 2.5. Mitsubishi's DDR SDRAM supports CL 1.5, CL 2 and CL 2.5 with burst lengths of 2, 4 and 8 for each data pin.