Motorola Readies Fastest, Low Power DSP With Large On-Chip SRAM

If your design team is developing computing platforms going into the hottest communications infrastructure markets, Motorola Semiconductor's (Austin, TX) announced addition to its ever-expanding DSP56300 digital signal processor family will likely have to be factored into your DSP choice decisions. That's especially true as Motorola starts sampling hardware in the third quarter and goes into production with its speediest low power DSP by year's end.

It's also likely the firm's DSP developments will significantly impact OEM developers even more now that Motorola Semiconductor Products Sector has joined forces with DSP powerhouse Lucent Technologies' Microelectronics Group. Together, the two companies enjoy the biggest slice of the worldwide programmable DSP marketplace pie, clobbering Texas Instruments (TI) in terms of market share.

The Silicon

Offering a smashing 255 MIPS of raw performance as an extensible 16- or 24-bit machine, Motorola's latest silicon, dubbed the DSP56311, looks more like a memory chip than a DSP. The fixed-point DSP56311 packs a hefty three Mbits of on-chip SRAM. That's 128 kwords (each is a three-byte, or 24-bit word). In many applications, this much on-chip SRAM will eliminate the need for external memory ICs, and also sidestep those pesky wait states needed to access such external memory.

When it becomes available, Motorola's DSP56311 will continue to propel the world of DSP design towards greater integration, a critical factor for systems housed in limited-space racks. These typically include cellphone systems that are remotely located at sites with no room for transceiver cabinet expansion. The same is true for telecommunications switches, high-speed network processors, and modem-bank racks. Designers of these types of systems need to put more bang in existing sized cabinets—and keep heat under control.

For DSP silicon vendors, the idea is to get more channels processed per chip. That spells more channels per board--and more channels per switching system.

Head-On Competition With TI

In the race to win the hearts and minds of telecomm DSP systems designers, Motorola is competing head-on with TI and its popular TMS320C5400 line. To do it, Moto is taking advantage of its HiP4DSP deep-submicron manufacturing processes for the DSP56311.

HiP4DSP brings several enhancements to the party. For one, the DSP56311's L-effective is now 0.18 microns. Also, while predecessor Motorola DSPs had metal geometries of 0.32 microns, the HiP4DSP process reduces that to 0.23 microns, a feature-size shrink that lends itself to lower dissipation and higher clock rates. That's the stuff that can help you meet tight dissipation and thermal budgets.

"Nonetheless, it's a challenge for us to balance the requirements for a DSP like this, "admits Arie Brish, digital systems operation manager for Motorola's Wireless Infrastructure System Division. "We have to tradeoff and optimize things like internal memory size, code density, data precision, I/O bandwidth and package size. We also need to supply a combination of application software development tools coupled with control code friendliness."

Parallel Processing

Brish notes that the 56311, which is packaged in a 196-pin plastic ball grid array, or PBGA, also includes what's called an enhanced filter coprocessor. The 150 MHz EFCOP hardware processes repetitive filter algorithms in parallel with core DSP routines, speeding compute-intensive functions such as echo canceling and voice coding. This is the kind of functionality that emerging high-speed wireless, and wireline—infrastructure as well as Internet telephony, applications need. The goal is to let a single DSP handle several voice and data channels simultaneously.

Thanks to its high degree of integration, Motorola's DSP will also tout a single-clock-cycle-per-instruction processing engine, as well as a 56-bit barrel shifter, an instruction cache, and a six-channel DMA controller. Also on-chip are will be a pair of Enhanced Synchronous Serial Interfaces (ESSIs), and an eight-bit parallel Host Interface (HI08) that will support a variety of buses with a glueless connection to industry-standard micros and DSPs.

The DSP56311 will also pack a Serial Communications Interface (SCI) with dedicated baud rate generator, and a triple timer module. The chip will let you set it up to accommodate up to 34 programmable pins of general purpose I/O (GPIO) too.

Compatibility Is Maintained

Brish also notes that the new DSP maintains compatibility with all previous Motorola DSP56300 devices, including application code, simulation models and most development tools. Because the device is object code compatible with the DSP56300 and DSP56000 families, it offers OEMs a migration path from the '56303, '309, and even the firm's '307 (which is presently supplied to only one large OEM). Brish points that many OEMs will be able to be upgraded to the '56311 without board re-layout. "Only the power sources will need to be changed," he notes.

"The DSP56311 uses split power supplies to separate the I/O and peripheral sections, which operate at 3.3 V, from the processor core, which runs at 1.8 V. This lets the rest of a system maintain a 3.3 V external I/O environment while minimizing voltage and dissipation in the chip's internal logic."

Using a simulation of a GSM cellphone half-rate vocoder, Brish says Motorola benchmarked the DSP56311 at a power stingy 700 µA/MIP. Even as it sips current, Brish contends that OEMs will typically see 510 million effective MACs (multiply-and-accumulates) with only two DSP56311 chips.

"To do 500 million effective MACs with TI devices would demand three of their TMSC5416 chips," he says. "What's more, we expect to be delivering DSP56311 silicon by the fourth quarter of this year, but TI's schedule doesn't call for delivery until the second half of the year 2000." Brish says the DSP will be priced at about $34 in 50,000-piece quantities when it hits distributor's shelves.

Lining Up Support

While OEMs await these developments, Motorola is prepping all-important development tools. Its Suite56 software and integrated development environment (IDE) for the DSP56311 include a low-cost evaluation module (EVM) and a hardware platform. Motorola says its Suite56 in-house tools are complemented by a range of third-party wares, including Tasking's Embedded Development Environment, which includes compilers, assemblers and linkers, and a debugger from Domain Technologies.

Operating system (OS) support includes the RTXC RTOS (realtime operating system) from Embedded System Products, and the Wisp OS from Wind River Systems, among others. System simulation environments will be provided by Cadence, Synopsys and Mentor Graphics. DSP algorithm development support is expected from Mathworks and Hyperception. Support will embrace industry standard protocols such as IS-95, audio, and CDMA voice codecs, as well as algorithms for ISDN, fax modems, and the like.

Motorola's roadmap also includes support for Ethernet, PCI Bus, and Universal Serial Bus (USB) command converters. It expects optimization of its all-important compiler technology too, as well as graphical user interface (GUI) enhancements.

Hungry for more details? Contact Motorola, M/S OE-314, 6501 William Cannon Dr., Austin, TX 78735. Phone: (512) 895-8674.