New Design Methodology Breaks Custom IC Bottlenecks

Cadence Design Systems, Inc. (San Jose, CA) has announced a new methodology created to break the bottlenecks associated with traditional custom integrated circuit (IC) layout and boost designers' productivity by an order of magnitude or more. Named automated custom physical design (ACPD), the methodology centers on a design flow comprising a cluster of Cadence's IC implementation products, including Virtuoso XL, a connectivity-driven version of the company's market-leading layout editor.

Custom physical design has typically been a time-consuming process, requiring engineers to manually push polygons to create IC layouts for critical designs, such as memory, analog, and high-speed digital blocks. While the last 10 years have yielded significant advances in front-end design productivity, physical layout has not experienced similar gains—primarily because there has been no viable solution to automate custom design. On top of this, the number of transistors on a die has skyrocketed during the same period. As a result, custom layout has become a bottleneck in the design process.

ACPD, which is designed to solve this problem, is a complete methodology for automating custom layout at all levels of the design hierarchy. It enables layout designers to quickly attain results equal to or better than those achieved via conventional methods, resulting in significant savings in both productivity and layout size, as well as helping boost product quality and meet strenuous time-to-market windows. It can thus be used by anyone working on an electronic product containing critical structures that must be custom-designed—for example, microprocessors, programmable logic devices, and chips for wireless and graphical applications.

ACPD is an open platform that creates a formalized, disciplined approach to the hand-off of information between the circuit designer and the layout designer. Critical design information from the schematic, such as design constraints, design changes and circuit connectivity, is passed to the layout tool, where this information is used to pre-place and pre-route the design to the desired level of completion. All of this data, including the pre-placement and pre-routing information, is then transmitted to an automatic routing tool, which completes the necessary routing and then passes the updated information back to the layout tool. This process, which greatly speeds component generation and interconnect creation, can be iterated as necessary to complete the physical design, which is then put through post-layout simulation and verification.