OptEM Inspector
OptEM Inspector screens the physical IC layout, extracts the resistance and capacitance of the interconnects and devices, and reports any potential crosstalk and time delay problems found in the design. What is unique about OptEM Inspector is its capability to extract device substrate resistance in addition to the interconnect resistance and fringe, area, and lateral capacitances. The substrate resistance and lateral capacitance are critical because of their effect on crosstalk at the submicron level. Both 2D and 3D electromagnetic field analysis techniques are used to accurately and efficiently extract these RC values from the layout.
OptEM Inspector's screening and extraction depend on technology and layout information provided by the designer. This includes a fabrication process description, active device definition, and GDSII data. Inspector runs a 2D or 3D field solution to determine the interconnect and device RC's. The choice of field solution depends on the level of accuracy required. On output, OptEM Inspector provides a SPICE circuit model of the extracted cells or nets and a screening report listing the cell hierarchy.
OptEM Inspector Features
- layout extraction includes multi-terminal devices, cross overs, edge and mutual capacitances, and contact resistances
- supports a library of high-level models of devices and sub-cells
- technology independent with user-defined element definitions
- analyzes the entire design or specific cells of the design
- operates in a hierarchical, flat, or mixed mode
- handles non-orthogonal layouts such as 45 degree geometries
- uses finite element resistance extraction and automated electromagnetic field solvers for greater accuracy
- generates per-net reports which can be sorted and filtered based on user specifications
- generates a standard SPICE netlist of devices and their interconnects
- run time is linear to the size of the layout which produces fast run times
- economical use of computer memory
- uses standard Motif graphical user interface to define input and to view output
- provides batch mode processing
- supports standards such as GDSII and SPICE
OptEM Inspector Benefits
- permits accurate simulation of the effects of the layout on the performance of the circuit
- accurate modeling of the circuit along with the effects of the interconnects
- capable of handling digital, analog, or mixed designs using MOS and/or bipolar technology
- determines critical nets and characterizes cell when migrating from one process to another
- flexible in trading memory and disk requirements versus accuracy and calculation time
- allows for the maximum flexibility in confidently developing effective designs
- applicable to high performance sub-micron, critical analog, and mixed analog/digital designs
- quickly determines problem nets based on criteria that are considered crucial to the performance of the design
- provides detailed simulation in SPICE to determine time delays and signal integrity effects
- usable for on-line use in an interactive design environment
- capable of handling large layouts
- easy to learn and use for frequent or casual users
- allows for hands-off operation where calculations can proceed even when not logged in
- provides easy integration with a user's current design environment and tools
OptEM Engineering Inc., 100 Discovery Place One, 3553- 31 Street NW., Calgary, AB T2L 2K7. Tel: 403-289-0499; Fax: 403-282-1238.