Palmchip Spins SOC Memory Sub-system Core

On-screen-configurable microprocessor cores are all the rage these days, with the likes of Tensilica (Santa Clara, CA), ARC (Middlesex, England), and Palmchip (San Jose, CA) pitching OEMs a variety of options and approaches for so-called systems-on-a-chip (SOC) designs. Today, Palmchip is introducing a line of parameterizable intellectual property (IP) cores for SOCs.

The firm's QuickConfig product series features a Web-based graphical user interface (GUI) environment for configuring the cores (Palmchip says you can use it to set up a core in mere minutes).

"The first generation of IP cores consisted of hard macros," notes Jauher Zaidi, the company's president and CEO. "The second generation brought about synthesizable IP cores. With this introduction, we're moving the SOC industry to the third generation of IP cores where IP is parameterizable through a GUI toolset."

Divide And Conquer

Palmchip's methodology divides an SOC into five major subsystems. These include a processor sub-system, memory sub-system, I/O sub-system, analog sub-system, and application-specific sub-system.

The first product in the QuickConfig series to support the divide-and-conquer approach is called the QuickConfig SOC Memory Sub-system core. It's a "megacore" that integrates a memory controller, an arbiter, a DMA controller, and a processor interface. Naturally, all are user-configurable. The core is a channel-based architecture that provides high bandwidth and low latency.

Key Partners

Palmchip is also currently working with several key partners and some of its own customers to incorporate its QuickConfig SOC Memory Subsystem core into SOC products. In particular, Palmchip is leveraging its existing CoreFrame Architecture with Synopsys's (Mountain View, CA) coreBuilder toolset. Indeed, QuickConfig was created using coreBuilder and is now delivered by Palmchip with Synopsys' free companion tool called coreConsultant.

CoreConsultant guides you through a series of steps to automatically configure the precise core configuration needed for your SOC. In addition, it automatically configures a high-speed simulation model (the company says it will work with all popular commercial simulators). The coreConsultant tool then runs synthesis automatically to produce an optimal gate-level netlist for layout.

Palmchip expects that the combo of the core design and the automated delivery tool will enable you to assemble complete SOCs quickly, dramatically reducing total design time.

Zaidi says the QuickConfig Memory Sub-system core is fully synthesizable and process portable, providing designers with technology and foundry independence. "SOC devices typically interface to external commodity memory," he notes, "which provides cost effective code and data storage for today's memory hungry operating systems. But, the memory interface must meet complex device timing requirements and optimize memory utilization.

"To assist OEMs to do that, the QuickConfig Memory Sub-system core supports all common memory device types including PC1OO and PC133 SDRAM, EDO DRAM, SRAM, flash and ROM. It also accommodates embedded memory blocks."

Zaidi bills it as a "drop-in solution" that can be configured using core parameters to meet the needs of a target application. "It will permit SOC designers to accelerate design schedules and focus on adding customer value and product differentiation," he says.

Palmchip says its QuickConfig Memory Sub-system is also designed to maximize memory bandwidth. It supports up to eight banks of memory, which can be any combination of device types. Moreover, memory data widths can be set independently for each bank at eight-, 16- or 32-bits, with automatic byte steering performed by the core data path.

Independent DMA Channels

A back-side interface also provides up to eight independent DMA channels to either a CoreFrame MBus, Advanced RISC Machines's AMBA Advanced System Bus (ASB), and the AMBA 2.0 Advanced High-Performance Bus (AHB). The interface also offers programmable hidden arbitration, DMA-to-memory burst matching (DMA burst length of 64 can be matched to an SDRAM burst of eight), and support for different DMA/memory clock domains. "This permits designers to control the feature set and generate highly gate-efficient designs," contends Zaidi.

Zaidi adds that Palmchip is also committed to making the technology available across the firm's GreenLogic IP core family as well as through its DirectConnect Partners' IP core offerings. Palmchip is also an active participant in the Virtual Socket Interface Alliance. VSIA was formed to ensure compliance with future standards for design re-use.

For more info, contact Zaidi at Palmchip Corp., 2055 Gateway Pl., Suite 240, San Jose, CA 95110. Phone: (408) 487-8696. Fax: (408) 573-7357.