Specman Elite - Testbench Automation
- Captures executable specifications
- Constraint-driven test generation
- Data and temporal checking
- Functional coverage analysis
- HDL simulator interfaces
- HW/SW co-verification support
Today's methods of verification just can't keep pace. Only a few iterations for debugging are acceptable as time-to-market windows shrink. To achieve first time success you can no longer hope that mass quantities of simulation or emulation uncover the underlying problems.
Verisity's Specman Elite offers you a comprehensive environment for all aspects of verification: automatic generation of functional tests, data and temporal checking, functional coverage analysis, and HDL simulation control.
But We Already Do That in `C', VHDL, Verilog...
You may already have invested time and effort on internal solutions, but realistically these ``tools" are rewritten project to project without allowing for significant reuse. They also don't contain the engines already built into Specman Elite, such as Verisity's patented Constraint-Solver, which allows fast and easy test generation—built in!
Verisity Solution
With Verisity's Specman Elite, you capture the rules from the specifications and use this info to automate the functional verification process. Specman Elite's methodology finds the ``bugs" you ``haven't thought of"— ambiguities in the spec, unanticipated usage by the target system. The result? Faster verification and higher quality products. Get working silicon to market on time!
Specman Elite is a comprehensive system for functional verification that automates the entire process of verification.
Captures Executable Specifications
Our powerful verification language e allows you to capture the rules from specifications as well as generate tests automatically. Specman Elite eliminates misinterpretation of specifications.
Constraint-Driven Test Generation
With Specman Elite's constraint-driven test generation, you can now automatically generate tests for functional verification. By specifying constraints, you can quickly and easily target the generator to create any test in your functional test plan. These tests are generated on-the-fly based on the current design state, making it possible to generate even hard-to-reach corner cases.
Data and Temporal Checking
Powerful temporal constructs enable you to capture complex protocols for checking. On-the-fly data checking and generation allows context-specific expected values. You can use any combination of gray/black/white box checking to speed debugging.
Functional Coverage Analysis
An executable functional test plan measures the progress of verification. Functional analysis automatically identifies holes in the test coverage. Verification schedules become more predictable because functional coverage is a meaningful and direct measure of the completeness of your verification.
HDL Simulator Interfaces
All leading VHDL and Verilog simulators are integrated with Verisity's Specman Elite. Internal signals of the device under test can be sampled and driven. 100 percent controllability and observability of otherwise inaccessible internal signals allows all engines of Specman Elite full access to signal values during the simulation.
Hardware/Software Co-Verification Support
All leading HW/SW co-verification tools are supported. For example, Mentor Graphics' Seamless co-verification environment is deeply integrated to enable functional testing of both hardware and software. Early integration and debugging of hardware /software systems will eliminate errors and shorten time to market for the combined system.
Verisity Design, Inc., 2041 Landings Drive, Mountain View, CA 94043. Tel: 650-934-6800; Fax: 650-934-6801; E-mail: rchope@verisity.com or jen@verisity.com.