STMicroelectronics' Latest STripFETs Sport Reduced On-Resistance and Gate Charge
The key to the differentiating properties of the STripFET devices is the single-feature-size process based on ST's patented strip-layout technique. Conventional power MOSFET processes are critically dependent on three cell dimensions, which means that attempts to reduce on-resistance by shrinking cell geometries lead to more complex and expensive processes. In contrast, the single-feature-size process needs fewer process steps and its only critical parameter is the width of the strip, which depends solely on the equipment resolution.
By optimally exploiting the capabilities of the wafer steppers and including a special Rapid Thermal Diffusion process, the NF series offers a 60% increase in channel perimeter compared to first generation STripFETs. This leads to higher current density and therefore to ever-decreasing on-resistance values as low as 2.5 for the STV160NF02L and STV160NF03L, which are 20-V and 30-V devices, respectively, and are housed in the PowerSO-10 package. The two MOSFETs are particularly suitable for high-efficiency DC-DC converters in telecom and computer applications. Other key benefits of the new technology include superior ruggedness and the ability to withstand much higher unclamped current densities than industry standard products.
The NF series initially comprises over 20 devices housed offered in a variety of through-hole and surface mounting packages, with breakdown voltages from 20 to 55V and current capabilities from 2 to 160A. The range also includes n-channel and p-channel devices housed in DPAK, D2PAK, SO-8, and SOT23-6L packages in a diverse variety of configurations. These products are particularly well suited for use in synchronous buck regulators for desktop PCs, such as the STB70NF03L, and mobile PCs (STS11NF03L in SO-8), thanks to the optimal trade-off between on-resistance and gate charge.
Edited by David Maliniak