SureCov - Automatic FSM, Expression, and Code Coverage
- Easy to use
- Automatic FSM analysis
- Intuitive block, arc, and toggle coverage
- Unique expression coverage
- Regression analysis utilities
- Lowest simulation overhead
With Verisity's SureCov, you see graphically which modules have been sufficiently exercised and which require additional effort. With this measure of effectiveness of your functional test suite, you can predict how much effort remains and your verification engineers can clearly see which sections of the design have not yet been adequately covered.
But What About the Overhead?
Has code coverage been so expensive that it is done too late or not at all? But all of the tests created for verification need to be evaluated to get an accurate picture of the verification status. Some tests may be unnecessarily redundant and take up valuable simulation time. Other tests may incompletely exercise portions of the design that will be synthesized to silicon.
Verisity Solution
You don't want to have a special version of your Verilog HDL for coverage analysis. With Verisity's SureCov you don't need one. SureCov automatically extracts the FSM from your Verilog without any code modifications. It's easy to use and it's fast!
Easy to Use: No changes to Source
No human intervention required. Design engineers can run this tool and do it in the course of performing design debug. Color-coded bubble diagrams and source code clearly show which sections of the design remain to be adequately covered.
Automatic FSM Analysis
By automatically recognizing common Finite State Machine types from the Verilog RTL design description, SureCov eliminates the tedious manual preprocessing required in some tools. The Verilog HDL can be visualized as a bubble diagram without any user intervention. SureCov paints the states and transition arcs in clear colors indicating tested, untested, and partially tested. The user can define paths thru FSMs and query the SureCov database to check coverage for the FSM paths.
Intuitive Block, Arc & Toggle Coverage
The most intuitive display of a text-oriented design is often in the original code. SureCov displays block, arc, and toggle coverage highlighted right in your code where it belongs. SureCov colors the lines entirely tested green, and those untested red. Code that has been executed but not from all possible combinations is yellow.
Unique Expression Coverage
In multi-term expressions, SureCov allows you to determine which terms contribute to a true value for the expression's On Terms and which terms contribute to a false value for the expression's Off Terms. A minimized sum of products and product of sum analysis is provided for each expression. SureCov displays expression and event coverage right in the code or, by clicking on the source, takes you to the expression detail of the terms.
Regression Analysis Utilities
SureCov has many utilities for test analysis and optimization. This includes a coverage API which enables reactive test generation.
Lowest Simulation Overhead
Helps you shorten time to market by doing verification quickly. SureCov provides comprehensive coverage analysis with the lowest possible simulation overhead. By analyzing the source code without burdening the simulator, typical overhead is 3x less than other coverage tools.
Verilog HDL
Analyzes Verilog HDL design descriptions and measures coverage for all possible code blocks, arcs, expressions and events. Supports Verilog-XL, NC Verilog, VCS, Polaris, ModelSim, and Silos III.
Links to SureSolve
Using SureSolve, together with SureCov, you can automatically generate a test suite to cover the parts of your design not yet tested. SureSolve uses white-box functional verification automation techniques to analyze a design, then automatically and intelligently build a test suite to fully exercise the design.
Verisity Design, Inc., 2041 Landings Drive, Mountain View, CA 94043. Tel: 650-934-6800; Fax: 650-934-6801; E-mail:rchope@verisity.com or jen@verisity.com.