Product/Service

SureLint - Static Design Analysis with Race Condition and FSM Analysis

Source: Verisity Design, Inc.
Designers need tools to analyze and debug their designs before integrating with the rest of the project. SureLint offers finite state machine (FSM) analysis, race detection, and many additional checks — the most complete lint tool on the market
How good is my design? Is my Verilog code clean and ready to integrate? Designers need tools to analyze and debug their designs before integrating with the rest of the project. SureLint offers finite state machine (FSM) analysis, race detection, and many additional checks — the most complete lint tool on the market.
  • Improved productivity and quality
  • Race detection
  • FSM analysis
  • Design reusability
  • Coding style standardization

With Verisity's SureLint, you can analyze and debug your designs, before going to simulation. Using simulation to debug your designs can be inefficient and often ambiguous. Simulators are designed to simulate HDL code as fast as possible, that means they skimp on the error messages, leaving you to figure out the error.

But My Synthesis and Simulation Tools Already Do That
Simulation and synthesis tools check code for certain types of static errors. But the two technologies analyze designs differently and don't necessarily find bugs and inefficiencies due to coding styles. This leads to bugs found late in the process where they are harder to fix and extremely costly.

SureLint identifies race conditions and automatically generates a race flow diagram so the cause of the race condition can easily be determined.

Verisity Solution
Verisity's SureLint is a next-generation static design verification software designed to analyze and debug your design prior to simulation to increase the quality of your design code and speed your overall verification. What sets SureLint apart from all other lint checkers is its unique race detection technology which can statically detect race conditions prior to simulation; and its finite state machine (FSM) analysis technology that lets you see complex state machines that may have unintended behavior. SureLint fits easily into existing design flows and works with all existing functional verification techniques and Verilog designs.

Race Detection
A major source of critical bugs in integrated circuit and intellectual property designs is simulation race conditions. A race condition can occur whenever syntactically correct HDL code produces a situation where the value of a circuit node is ambiguous, and can be evaluated differently by various simulators. This results in RTL design behavior being simulator dependent, and can lead to difficult-to-find differences between RTL and gate-level behavior.

Diagnosing race conditions has previously required long simulation runs, with test vectors that, by luck, exercise them. SureLint includes a new, unique static analysis technology which allows the detection of potential race conditions prior to simulation. These race conditions are displayed graphically so that the cause of the race condition can be easily determined.

FSM Analysis
SureLint uses Verisity's finite state machine recognition techniques to automatically (no comments, pragmas or source code modifications needed) extract FSMs from the source code. After extraction, the FSMs are analyzed for redundant, unreachable and terminal states. The FSM analysis results are available on a state diagram for easy viewing.

SureLint offers FSM extraction and bubble diagram drawing capabilities. Surelint was designed for fast easy-to-use analysis and debugging capabilities. With SureLint, you can check your code before running it through a simulator and save valuable simulation time while increasing the quality of your HDL.

Rules Checking
SureLint includes five additional types of conventional rules checks: syntax, standard lint, coding style, simulation and synthesis. These checks help you reduce downstream simulation and synthesis errors, and provide a measure of consistency for diverse design teams.

Ease of Use
SureLint runs both from the command line and the graphical user interface (GUI). The GUI provides an interactive results display, allowing the user to click on a message from SureLint and be transported to the design code that caused that message. Various filtering mechanisms allow you to view only what is important to you. In addition, FSMs are viewed as bubble diagrams, and race conditions are also displayed graphically.

Usage
SureLint works with all Verilog designs. It runs on Unix, Linux and Windows NT.

Verisity Design, Inc., 2041 Landings Drive, Mountain View, CA 94043. Tel: 650-934-6800; Fax: 650-934-6801; E-mail: rchope@verisity.com or jen@verisity.com.