Understanding Jitter In-High Frequency Oscillators

What is it? How can it affect your design?

By Douglas Gay, ValpeyFisher Corp.

Frequency stability of quartz crystal oscillators that provide fundamental circuit timing is critical in Gigabit Ethernet, ATM, and other very high-speed circuit technologies. A crystal oscillator is generally considered to be the most desirable method for providing dependable clock signals with solid frequency stability.

Frequency Stability
There are three types of frequency stability to consider when choosing a crystal oscillator. They are:

• Long-term frequency stability, which is determined by aging of the crystal and other circuit components;
• Medium term frequency stability, which is determined by environmental influences such as temperature, vibration, and pressure;
• Short-term stability, where the frequency fluctuates around its nominal value over a short period (up to, say, 10 seconds).

For now we'll focus on short-term frequency stability, which is described by several interrelated parameters. Let's look at two of them, phase noise and then phase jitter. Both are important considerations for digital data transmissions.

Phase Noise
The most commonly used parameter describing short term frequency stability is phase noise. For an ideal sinusoidal signal, disturbances due to frequency and amplitude fluctuations give rise to a spectral bandwidth and noise sidebands as shown in Figure 1. The relative level of the noise sidebands defines the spectral purity of the signal. Phase noise is usually expressed as power at 1 Hz bandwidth at a particular frequency away from the carrier frequency.

Jitter
A second way to characterize short-term stability is phase jitter, which describes how phase variations cause fluctuations of the zero crossing of the carrier signal. For digital data communications, phase jitter is a more useful way to characterize short-term frequency stability because it provides a precise way to establish when a phase transition occurs.

For example, suppose we have a 100 MHz clock input. Data can be encoded by varying the phase of the rising edge of the clock signal at certain intervals. To maintain certainty that a given incident actually represents useful data and not just noise that is shifting the phase, there must be absolute certainty in the basic clock frequency at that particular period of time. If there is variation from period to period, there will be uncertainty as to whether data is encoded into the signal. The measure of that uncertainty is the phase jitter of the digital signal.

Jitter can be calculated from phase noise measurements by a formula that integrates the noise over different frequency offsets from the carrier signal frequency. The result is the RMS value of the frequency noise (or mean frequency fluctuation) expressed in units of time. Jitter thus represents a measure of the uncertainty of the phase, measured in picoseconds (or, if it's really bad jitter, in nanoseconds).

Scoping Out Jitter
To visualize jitter, refer to the screen of a digitizing oscilloscope set on infinite persistence with the time scale set at, say, 50 picoseconds. If all the rising edges from a constantly running signal at the same carrier frequency are captured and accumulated, the line on the scope has a certain width, which is an indication of the jitter-it says the rising edge jitters around its normal value. Figure 3A shows the measurement of a Valpey-Fisher crystal oscillator, where the width of the entire scale is 200 ps. Here the indication of jitter is limited by the instrument itself.

Competitive methods for creating a 125 MHz clock frequency involve utilizing a PLL frequency synthesizer that runs at a basic clock speed of 25 MHz and then multiplying by a factor of five. Although mid-term or long-term accuracy will be determined by the 25 MHz clock, short-term stability as determined by phase noise will degrade by the square of the multiplying factor-in this example noise power is multiplied by 25.

Phase jitter will depend on how the frequency is multiplied. If an analog multiplier is used, the end result is likely to be a substantial aggravation of the original jitter, since considerable power of subharmonics will be present. Potentially a PLL synthesizer can provide reasonably good performance compared to an analog multiplier. However, the basic jitter even before frequency multiplication varies widely compared to precision crystal oscillators. As seen in Figure 3B, the digitizing oscilloscope measuring jitter of a typical PLL synthesizer clock shows a spread of nearly the full 200 ps width of the screen.

Same Old GIG
What does this say? In Gigabit Ethernet (GbE) systems, the basic clock rate is 1.25 GHz (800 ps period). To establish this clock rate, a competitive 125 MHz PLL synthesizer must be multiplied by a factor of ten, which will substantially worsen an already jittery clock frequency, creating huge uncertainties that might result in data glitches. It may work OK on one board, but not on another. Or work OK on a given board now, but not later.

Summary
At very high frequencies, sensitivity to errors is heightened in every part of a design. A low phase jitter clocking source can provide cost and accuracy benefits for an entire system by allowing designers more room to maneuver in other critical areas of the design that are possibly even more costly.

ValpeyFisher Corporation, 75 South Street, Hopkinton, MA 01748. Tel: (800) 982-5737; Fax: (508) 435-5289; e-mail:dsg12metre@aol.com.